library verilog;
use verilog.vl_types.all;
entity cmsdk_mcu_stclkctrl is
    generic(
        DIV_RATIO       : vl_logic_vector(0 to 17) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi1, Hi1, Hi1, Hi1, Hi0, Hi1, Hi0, Hi0, Hi0);
        DIVIDER_RELOAD  : vl_notype
    );
    port(
        FCLK            : in     vl_logic;
        SYSRESETn       : in     vl_logic;
        STCLKEN         : out    vl_logic;
        STCALIB         : out    vl_logic_vector(25 downto 0)
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of DIV_RATIO : constant is 1;
    attribute mti_svvh_generic_type of DIVIDER_RELOAD : constant is 3;
end cmsdk_mcu_stclkctrl;
